introduction
--- Smart Card (SmartCard), also known as Integrated Circuit Card (IC card), combines microelectronic technology and computer technology, with high reliability, security and flexibility, which is widely used. In the fields of telecommunications, finance, transportation and public utilities. The smart card interface controller is a bridge connecting the smart card and the master device, and is one of the most important components in the smart card processing device. Faced with huge market demand, major chip manufacturers have introduced their own smart card interface controller chips, such as Philips' 8007, Linear's LTC1755/6 and so on. This paper also proposes a practical design of a smart card interface controller.
How the controller works
â— Structure of the controller
--- The design process of this solution follows the general flow of integrated circuit design, using a top-down modular design approach. The controller consists of seven sub-modules: Card Activation Reset Module (RSTM), Serial Data Transceiver Module (RxTxM), Status Interrupt Management Module (INTM), Timing Module (TM), Clock Management Module (CLKM), Register Address Management Module (AM) and main controller interface (IF). Its structure is shown in Figure 1. CLKC, IOC, PRESC, VDDC and RSTC are the interfaces of the controller and the smart card. They are the clock output to the smart card, the bidirectional data line, the card presence input signal, the card power control signal and the output card. Reset signal. The interface signals of the controller and the main controller (such as CPU) are: main clock input CLK, address signal A, bidirectional parallel data line D, chip select input signal CS, write control signal WR, read control signal RD, main reset signal RST and interrupt output signal INT.
â— Internal register
--- Generally, the user program can realize the transaction with the IC card through the read and write operation of the card interface controller register. Therefore, the rationality of the internal register setting of the smart card controller directly affects the feasibility and future of the design scheme. The convenience of using the actual product. The register settings of different smart card controllers are generally different. Compared with other smart card controllers, the number of registers set in this solution is relatively large and the functions are more comprehensive. Table 1 lists the registers of this controller and their address assignments.
--- The card controller enable register EN acts like a master switch to enable or disable the entire controller. When the user system does not need to use the card controller temporarily, you can set EN=0 to turn off all operations inside the entire controller (including the internal frequency divider), which can reduce unnecessary power consumption in the system. The setting of the clock prescaler parameter register PRSCL allows the controller to be easily applied to a target system with a high clock frequency without the need for an external divider. Currently, most other card controllers do not have registers with the same or similar functions as EN and PRSCL. Therefore, the setting of the register EN and PRSCL is a major feature of this solution. If this card controller is used as an IP in the design of the SoC, this feature will be particularly important.
---Work wait time The integer value register WWT is valid only for the T=0 class card. The character wait time integer value register CWT and the block wait time integer value register BWT are only valid for the T=1 class card. The controller also sets these three registers at the same time, so it can communicate with the T=0 class card and the T=1 class card, thus making up for most of the current card interface controllers. The drawback of a certain type of card to communicate.
--- As shown in Table 1, the controller also sets other registers, such as ETU, TXDB, STMR, etc., in order to more fully meet the requirements of the ISO7816-3 standard, and is compatible with all types of IC cards, while making User software can more easily intervene in the transaction process with the IC card, improving the controllability and ease of use of the transaction process.
â— The working process of the card controller
--- The main controller (HOST) sends a command to the card controller through the main controller interface (IF) (ie, the register of the operation card controller), and each module of the card controller cooperates to parse the command and then passes the IC. The card interface performs corresponding operations on the card, thus completing the primary controller's operation on the IC card. Similarly, the command or status from the IC card is processed by the card controller, and the related information is reported to the main controller. This is how the card controller acts as a bridge between the IC card and the main controller. The following will focus on the working process of the serial data transceiver module (RxTxM).
--- The serial data transceiver module (RxTxM) of the card controller designed by this scheme is responsible for receiving the serial data sent by the IC card and transmitting the commands of the main controller to the IC card in a serial manner. The serial data receiver is a state machine, and its state transition diagram is shown in Figure 2. The state machine is usually idle (idle). If there is no negative transition (NoFallingEdge) on the IOC port, the state machine will remain in this state. When a negative pulse (FallingEdge) is detected on the IOC, the state machine enters the start bit state (startbit). If the start bit is invalid (StartBitInvalid, for example, the width is insufficient), the state machine returns the idle state, otherwise the state machine Enter the receive data state (data). If 8 bits of data have not yet been filled (CntBit<8), the reception continues. If 8 bits of data have been filled (CntBit=8), the state machine enters the state of receiving and verifying parity. If the parity does not end (Checking), the processing continues, otherwise the state machine returns the idle state, and the controller completes a receiving process.
--- If it successfully receives 1 byte, it will immediately generate a successful receiving state quantity rcv_ok, and submit it to the state interrupt management module (INTM); if the received data has an error, it will immediately submit the receiving error status rcv_error to INTM, and generates a negative pulse of 1 to 2 bits of data width on the IOC data line to request the IC card to resend the previous byte. According to the ISO7816 standard, this retransmission request for the same 1-byte is transmitted only at most three times. Therefore, if RxTxM still receives the wrong byte after the third retransmission request, RxTxM immediately generates a status RTO that is overrunned and reported to INTM.
---When the master writes 1-byte data to the number of registers in the controller, the controller will send it to the IC card in serial mode. If the transmission is successful and no retransmission of the IC card is detected. The request immediately generates a successful status quantity tr_ok, which is reported to the status interrupt management module; if an IC card retransmission request is detected, the previous byte is retransmitted. Similarly, if the resend request of the IC card is still received after the third retransmission, the INTM is immediately reported to a state in which the number of retransmissions is exceeded.
Design simulation and implementation â— Timing simulation of the controller model
--- In the ISE5 integrated development environment of Xilinx, the RTL model of each module is established by VHDL language, and the test vector testbench is written in VHDL, and the external simulation software Modelsim is used for simulation. Due to the length of the relationship, only the simulation timing waveform when the controller receives the serial data sent by the IC card is listed here, as shown in FIG.
--- As can be seen from Figure 3, the serial data sent by the IC card is 1001001010 (lower bit first), a total of 10 bits, except the start bit 0 and the check bit 1, the 8-bit data is 00100101, and the data is received. The contents received by the register rxbuffer are the same, and the check result is 0, which satisfies ISO 7816.
â— Designed FPGA implementation
--- According to the comprehensive results, the target device uses Xilinx's Spartan2 series of xc2s30tq144-6, and its internal resources are listed in Table 2.
--- In order to further verify the correctness of the design, the interface of the controller model is changed to the APB interface of the AMBA bus, and it is connected as a peripheral IP to the APB bus of the SoC with the AMBA bus as the internal bus, and then The SoC system is compiled and downloaded into the FPGA, embedded in the actual application system, and verified to be able to trade with the IC card.
in conclusion
--- The feasibility of the IC card controller designed by this scheme has been verified in practical applications. The application software can conveniently communicate with the smart card through the operation of the internal registers of the controller. The IC card controller can be separately downloaded to the FPGA or CPLD device and applied to the target system. After modifying the external interface, it can be used as an IP module for easy application to the SoC system. Go in the design. Since there is no built-in power module for powering the IC card, in practical applications, it needs to be used together with the external power module, which needs further improvement and improvement.
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